1. Field of the Invention
The invention relates to a single-to-differential conversion circuit, more particularly to a single-to-differential conversion circuit with gain compensation.
2. Description of the Related Art
In a telecommunication system, the receiver usually needs to use a single-to-differential conversion circuit to convert a received radio frequency (RF) signal into a differential signal having a first differential voltage and a second differential voltage. Under ideal conditions, the first and second differential voltages should be the same in magnitude, and 180° out of phase.
Looking at the current technology of the related circuit and the small signal model for a single-to-differential conversion circuit as shown in FIGS. 1 and 2, a simple description is provided as follows:
After a first transistor M1 receives a RF signal, under ideal conditions and when the equivalent impedances Zgs1, Zgs2, Z3 (where Zgs1 is the equivalent impedance between the gate and source of the first transistor M1, Zgs2 is the equivalent impedance between the gate and source of a second transistor M2, and Z3 is a third equivalent impedance) are sufficiently large in magnitude (or the equivalent impedances Zgs1, Zgs2, and Z3 approach positive infinity), and when the load equivalent impedance ZL is sufficiently small in magnitude, the single-to-differential conversion circuit can output a first differential voltage Vo1 and a second differential voltage Vo2 as follows:
            V              o        ⁢                                  ⁢        1              =                  -                              g            m                    ⁡                      (                                          V                1                            2                        )                              ⁢              Z        1                        V              o        ⁢                                  ⁢        1              =                            g          m                ⁡                  (                                    V              1                        2                    )                    ⁢              Z        2            
Where Z1 is a first equivalent impedance, Z2 is a second equivalent impedance, V1 is an input voltage, and gm is a transconductance coefficient of the first transistor M1 (or the second transistor M2). In the implementations of the current technology, the first and second equivalent impedances Z1, Z2 are implemented by resistors, and the third equivalent impedance Z3 is implemented by resistors or transistors.
Therefore, under ideal conditions, when the first equivalent impedance Z1 is equal to the second equivalent impedance Z2, the single-to-differential conversion circuit will output a group of differential voltages including the first differential voltage Vo1 and the second differential voltage Vo2. When the first differential voltage Vo1 and the second differential voltage Vo2 are equal, the phase difference is 180°.
However, during the operation of the single-to-differential conversion circuit described above, the input voltage V1 is usually attenuated when transmitted to a node X because the equivalent impedance Zgs1 between the gate and the source of the first transistor M1, the equivalent impedance Zgs2 between the gate and the source of the second transistor M2, and/or the third equivalent impedance Z3 are not large enough. The magnitude of the voltage Vx at the node X is thus smaller than half the input voltage V1, and the gate-source voltage Vgs1 of the first transistor M1 is therefore not equal to the gate-source voltage Vgs2 of the second transistor M2. The gain mismatch of the first and second differential voltages Vo1, Vo2 in the set of differential signals will result in unbalanced set of differential signals. Therefore, it is worth looking into efficiently solving the gain mismatch problem when designing the receiver circuit of a telecommunication system.